industrial temperature range idt74alvch162373 3.3v cmos 16-bit transparent d-type latch with 3-state outputs 1 july 2009 industrial temperature range idt and the idt logo are registered trademarks of integrated device technology, inc. ? 2009 integrated device technology, inc. dsc-4575/6 features: ? 0.5 micron cmos technology ? typical t sk(o) (output skew) < 250ps ? esd > 2000v per mil-std-883, method 3015; > 200v using machine model (c = 200pf, r = 0) ?v cc = 3.3v 0.3v, normal range ?v cc = 2.7v to 3.6v, extended range ?v cc = 2.5v 0.2v ? cmos power levels (0.4 w typ. static) ? rail-to-rail output swing for increased noise margin ? available in ssop and tssop packages functional block diagram description: this 16-bit transparent d-type latch is built using advanced dual metal cmos technology. the alvch162373 is particularly suitable for imple-menting buffer registers, i/o ports, bidirectional bus drivers, and working registers. this device can be used as two 8-bit latches or one16-bit latch. when the latch enable (le) input is high, the q outputs follow the data (d) inputs. when le is taken low, the q outputs are latched at the levels set up at the d inputs. a buffered output-enable ( oe ) can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. in the high-impedance state, the outputs neither load nor drive the bus lines signifi- cantly. the high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. oe does not affect internal operations of the latch. old data can be retained or new data can be enetered while the outputs are in the high-impedance state. the alvch162373 has series resistors in the device output structure which will significantly reduce line noise when used with light loads. this driver has been designed to drive 12ma at the designated threshold levels. the alvch162373 has ?bus-hold? which retains the inputs? last state whenever the input goes to a high impedance. this prevents floating inputs and eliminates the need for pull-up/down resistor. drive features: ? balanced output drivers: 12ma ? low switching noise idt74alvch162373 3.3v cmos 16-bit trans- parent d-type latch with 3-state outputs and bus-hold 1 oe c1 1d 1 d 1 47 1 le 1 q 1 to 7 other channels 2 oe 2 d 1 36 2 le 2 q 1 to 7 other channels 1 48 2 24 25 13 c1 1d applications: ? 3.3v high speed systems ? 3.3v and lower voltage computing systems
industrial temperature range 2 idt74alvch162373 3.3v cmos 16-bit transparent d-type latch with 3-state outputs ssop/ tssop top view pin configuration 1 q 2 gnd v cc gnd gnd 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 40 41 42 43 44 45 46 47 48 1 1 q 1 1 oe 1 q 4 1 q 3 1 q 6 1 q 5 1 q 8 1 q 7 2 q 1 2 q 3 2 q 2 2 q 4 v cc 2 q 5 2 q 6 gnd 2 q 7 2 q 8 2 oe 1 d 2 gnd v cc gnd gnd 1 d 1 1 le 1 d 4 1 d 3 1 d 6 1 d 5 1 d 8 1 d 7 2 d 1 2 d 3 2 d 2 2 d 4 v cc 2 d 5 2 d 6 gnd 2 d 7 2 d 8 2 le note: 1. as applicable to the device type. symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 5 7 pf c out output capacitance v out = 0v 7 9 pf c i/o i/o port capacitance v in = 0v 7 9 pf symbol description max unit v term (2) terminal voltage with respect to gnd ?0.5 to +4.6 v v term (3) terminal voltage with respect to gnd ?0.5 to v cc +0.5 v t stg storage temperature ?65 to +150 c i out dc output current ?50 to +50 ma i ik continuous clamp current, 50 ma v i < 0 or v i > v cc i ok continuous clamp current, v o < 0 ?50 ma i cc continuous current through each 100 ma i ss v cc or gnd absolute maximum ratings (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v cc terminals. 3. all terminals except v cc . capacitance (t a = +25c, f = 1.0mhz) note: 1. these pins have "bus-hold". all other pins are standard inputs, outputs, or i/os. pin names description xdx data inputs (1) xle latch enable inputs x q x 3-state outputs x oe 3-state output enable input (active low) pin description inputs outputs x oe xle xdx xqx lhh h lhl l hxx z llx q o (2) notes: 1. h = high voltage level l = low voltage level x = don?t care z = high impedance 2. output level before the indicated steady-state input conditions were established. function table (each 8-bit section) (1)
industrial temperature range idt74alvch162373 3.3v cmos 16-bit transparent d-type latch with 3-state outputs 3 symbol parameter test conditions min. typ. (1) max. unit v ih input high voltage level v cc = 2.3v to 2.7v 1.7 ? ? v v cc = 2.7v to 3.6v 2 ? ? v il input low voltage level v cc = 2.3v to 2.7v ? ? 0.7 v v cc = 2.7v to 3.6v ? ? 0.8 i ih input high current v cc = 3.6v v i = v cc ?? 5a i il input low current v cc = 3.6v v i = gnd ? ? 5a i ozh high impedance output current v cc = 3.6v v o = v cc ?? 10 a i ozl (3-state output pins) v o = gnd ? ? 10 v ik clamp diode voltage v cc = 2.3v, i in = ?18ma ? ?0.7 ?1.2 v v h input hysteresis v cc = 3.3v ? 100 ? mv i ccl quiescent power supply current v cc = 3.6v ? 0.1 40 a i cch v in = gnd or v cc i ccz i cc quiescent power supply current one input at v cc - 0.6v, other inputs at v cc or gnd ? ? 750 a variation dc electrical characteristics over operating range following conditions apply unless otherwise specified: operating condition: t a = ?40c to +85c note: 1. typical values are at v cc = 3.3v, +25c ambient. bus-hold characteristics symbol parameter (1) test conditions min. typ. (2) max. unit i bhh bus-hold input sustain current v cc = 3v v i = 2v ? 75 ? ? a i bhl v i = 0.8v 75 ? ? i bhh bus-hold input sustain current v cc = 2.3v v i = 1.7v ? 45 ? ? a i bhl v i = 0.7v 45 ? ? i bhho bus-hold input overdrive current v cc = 3.6v v i = 0 to 3.6v ? ? 500 a i bhlo notes: 1. pins with bus-hold are identified in the pin description. 2. typical values are at v cc = 3.3v, +25c ambient.
industrial temperature range 4 idt74alvch162373 3.3v cmos 16-bit transparent d-type latch with 3-state outputs note: 1. v ih and v il must be within the min. or max. range shown in the dc electrical characteristics over operating range table for the appropriat e v cc range. t a = ? 40c to + 85c. output drive characteristics symbol parameter test conditions (1) min. max. unit v oh output high voltage v cc = 2.3v to 3.6v i oh = ? 0.1ma v cc ? 0.2 ? v v cc = 2.3v i oh = ? 4ma 1.9 ? i oh = ? 6ma 1.7 ? v cc = 2.7v i oh = ? 4ma 2.2 ? i oh = ? 8ma 2 ? v cc = 3v i oh = ? 6ma 2.4 ? i oh = ? 12ma 2 ? v ol output low voltage v cc = 2.3v to 3.6v i ol = 0.1ma ? 0.2 v v cc = 2.3v i ol = 4ma ? 0.4 i ol = 6ma ? 0.55 v cc = 2.7v i ol = 4ma ? 0.4 i ol = 8ma ? 0.6 v cc = 3v i ol = 6ma ? 0.55 i ol = 12ma ? 0.8 switching characteristics (1) notes: 1. see test circuits and waveforms. t a = ? 40c to + 85c. 2. skew between any two outputs of the same package and switching in the same direction. operating characteristics, t a = 25c v cc = 2.5v 0.2v v cc = 3.3v 0.3v symbol parameter test conditions typical typical unit c pd power dissipation capacitance outputs enabled c l = 0pf, f = 10mhz 19 22 pf c pd power dissipation capacitance outputs disabled 4 5 v cc = 2.5v 0.2v v cc = 2.7v v cc = 3.3v 0.3v symbol parameter min. max. min. max. min. max. unit t plh propagation delay 1.5 5.3 1.5 4.5 1.5 4 ns t phl xdx to xqx t plh propagation delay 2 5.6 2 5 2 4 ns t phl xle to xqx t pzh output enable time 1.5 6.5 1.5 6 1.5 5 ns t pzl x oe to xqx t phz output disable time 1.5 5.6 1.5 5.5 1.5 4.5 ns t plz x oe to xqx t su setup time, data before le 2?2?2?ns t h hold time, data after le 1.5 ? 1.5 ? 1.5 ? ns t w pulse duration, le high or low 3.3 ? 3.3 ? 3.3 ? ns t sk(o) output skew (2) ? ???? 500 ps
industrial temperature range idt74alvch162373 3.3v cmos 16-bit transparent d-type latch with 3-state outputs 5 open v load gnd v cc pulse generator d.u.t. 500 500 c l r t v in v out (1, 2) alvc link input v ih 0v v oh v ol t plh1 t sk (x) output 1 output 2 t phl1 t sk (x) t plh2 t phl2 v t v t v oh v t v ol t sk (x) = t plh2 - t plh1 or t phl2 - t phl1 alvc link same phase input transition opposite phase input transition 0v 0v v oh v ol t plh t phl t phl t plh output v ih v t v t v ih v t alvc link data input 0v 0v 0v 0v t rem timing input synchronous control t su t h t su t h v ih v t v ih v t v ih v t v ih v t alvc link asynchronous control low-high-low pulse high-low-high pulse v t t w v t alvc link control input t plz 0v output normally low t pzh 0v switch closed output normally high enable dis- able switch open t phz 0v v lz v oh v t v t t pzl v load/2 v load/2 v ih v t v ol v hz alvc link test circuits and waveforms propagation delay test circuit for all outputs enable and disable times set-up, hold, and release times notes: 1. for t sk (o) output1 and output2 are any two outputs. 2. for t sk (b) output1 and output2 are in the same bank. definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. notes: 1. pulse generator for all pulses: rate 1.0mhz; t f 2.5ns; t r 2.5ns. 2. pulse generator for all pulses: rate 1.0mhz; t f 2ns; t r 2ns. output skew - t sk ( x ) pulse width note: 1. diagram shown for input control enable-low and input control disable-high. symbol v cc (1) = 3.3v0.3v v cc (1) = 2.7v v cc (2) = 2.5v0.2v unit v load 6 6 2 x vcc v v ih 2.7 2.7 vcc v v t 1.5 1.5 vcc / 2 v v lz 300 300 150 mv v hz 300 300 150 mv c l 50 50 30 pf test conditions switch position test switch open drain disable low v load enable low disable high gnd enable high all other tests open
industrial temperature range 6 idt74alvch162373 3.3v cmos 16-bit transparent d-type latch with 3-state outputs ordering information xx alvc xxx xx package device type temp. range pvg pag 162 74 shrink small outline package - green thin shrink small outline package - green 16-bit transparent d-type latch with 3-state outputs ? 40c to +85c xxx family bus-hold 373 bus-hold double-density with resistors, 12ma h corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 logichelp@idt.com san jose, ca 95138 fax: 408-284-2775 www.idt.com
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